This invention relates to a multi-stage, low-offset, fast-recovery, comparator system and method and more particularly to such a system and method which minimizes undesirable offset voltages by utilizing an active negative feedback circuit which eliminates overdrive recovery delays.
Successive approximation analog to digital conversion systems (ADC""s) utilize a comparator to make a series of comparisons to determine a binary value for an analog input. Comparators are essentially a cascade of dual input amplifier stages which amplify the difference of the two input signals by a gain factor. There are several problems associated with these multi-stage comparator systems, namely any error which occurs at the input of the first amplifier in the series is going to be multiplied by the product of all the individual gains of the amplifiers used in the series. Specifically, if you have a multi stage comparator system which utilizes four amplifier stages, each having a gain of ten, any error which occurs on the input of the first amplifier will be multiplied by a factor of 10,000 (104). In a practical implementation, the output voltage would be limited by the circuit""s power supplies or more likely by some gain limiting clamping circuitry. As can be imagined, all errors which occur at the input to the first amplifier in the chain must be minimized.
During the conversion process, most of the comparisons are easy (non-critical) decisions where the input signal to the comparator is greater than the highest resolution (or least significant bit) of the ADC. However, some comparisons are more difficult (critical) decisions where the input signal is smaller than the least significant bit of the ADC.
A problem associated with these multi-stage comparator systems is that comparators have internal errors which frustrate their use in high precision systems. Specifically, every comparator has an internal voltage offset error (Voffset) which adds a small voltage to one of the comparator inputs. In a theoretical xe2x80x9cidealxe2x80x9d comparator, an input of zero volts applied to each of the comparator inputs (where the comparator has a gain of 1,000) would result in an output voltage of zero, as the difference between the two input signals is zero. However, since comparators have this internal Voffset error, one of the two input terminals will appear to have a slightly higher voltage then that which is actually present on its terminal. The amount of this voltage difference is known as the voltage offset error (Voffset). Typically, the offset voltage for an average comparator is in the range of 10-15 millivolts (10-15 mV). Therefore, in the event that a signal of zero volts is applied to both input terminals of a comparator (having a gain of 1,000), one input signal will be interpreted as the value of the offset voltage (e.g. 10 millivolts) which would result in an output of 10 volts (10 mV*1,000). In a practical implementation, the output voltage would be limited by the circuit""s power supplies or more likely by some gain limiting clamping circuitry.
Another problem associated with multi-stage comparator systems is excessive delay due to the overdriven condition that inevitably results from a non-critical comparison. If, in our example, the overdrive condition as described above is present on all four amplifiers, as it often is after a non-critical comparison, the overdrive recovery delay for the comparator will be essentially four times the delay of any one stage. This result will be explained in more detail below, but it is important to note that these additive overdrive recovery delays may dominate the factors limiting the speed of the comparator.
In an effort to reduce the speed limitation due to multiple overdrive recovery delays, various methods of resetting each stage of the comparator between each comparison have been employed, however with limited success.
In an effort to alleviate the problem of offset voltage induced output errors, one particular multi-stage comparator system utilizes a series of capacitors to AC-couple each comparator in the multi-stage comparator system. Since the offset voltage is a DC voltage, any offset voltage will be filtered prior to being applied to the input terminals of the individual comparators. However, this approach does not remove the offset voltage present at the output of each stage and, therefore, the overdrive recovery delays will make the system ill-suited for high speed data processing.
It is therefore an object of this invention to provide a multi-stage, low-offset, fast-recovery comparator system and method.
It is a further object of this invention to provide such a system and method which can be DC-coupled and minimizes overdrive recovery delay.
It is a further object of this invention to provide such a system and method which improves processing speed by reducing overdrive recovery delay.
It is a further object of this invention to provide such a system and method which can perform high-resolution conversion through the use of standard resolution components.
It is a further object of this invention to provide such a system and method which reduces offset voltage errors to usable levels.
This invention results from the realization that a truly effective multi-stage, low-offset, fast-recovery comparator system and method can be achieved by utilizing a series of amplification stages which minimizes input and output offset voltages through negative feedback.
This invention features a multi-stage, low-offset, fast-recovery, comparator system including: a plurality of self-correcting amplification stages connected in series, each amplification stage having a reset switch connected at its output for returning the output of each amplification stage to the operating input range of the next stage and providing fast response to its next input signal, each amplification stage including: a main amplifier, having a signal input terminal and an offset adjustment input, said main amplifier responsive to an input for generating an output; and a local feedback circuit, responsive to the output, for providing an offset adjustment signal to the offset adjustment input to compensate for the local offset voltage of the main amplifier.
In a preferred embodiment, the local feedback circuit may include a zeroing amplifier circuit, having an input terminal responsive to the output, for generating the offset adjustment signal. The zeroing amplifier circuit may include a zeroing amplifier offset reduction circuit to minimize the input offset voltage of the zeroing amplifier circuit. The zeroing amplifier circuit may have a zero adjustment input terminal, the zeroing amplifier offset reduction circuit including: a first switching means for applying the offset adjustment signal to the zero adjustment input terminal; and a second switching means for applying a predetermined zeroing signal to the input terminal of the zeroing amplifier circuit. The main amplifier may have an offset adjustment input terminal, the local feedback circuit further including: a first switching means for applying the offset adjustment signal to the offset adjustment input terminal of the main amplifier; a second switching means for applying the output of the main amplifier to the input terminal of the zeroing amplifier circuit; a third switching means for applying a zero input signal to the signal input terminal of the main amplifier; and a fourth switching means for applying the output of the previous amplification stage to the signal input terminal of the main amplifier.
This invention also features a multi-stage, low-offset, fast-recovery, comparator system including: a plurality of offset-corrected amplification stages connected in series, each amplification stage having a reset switch connected at its output for returning the output of each amplification stage to the operating input range of the next stage and providing fast response to its next input signal, where each amplification stage is DC-coupled to the next amplification stage in the series.
In a preferred embodiment, each amplification stage may include: a main amplifier having a signal input terminal and an offset adjustment input, said main amplifier responsive to an input for generating an output; and a feedback circuit, responsive to the output, for providing an offset adjustment signal to the offset adjustment input to compensate for the local offset voltage of the main amplifier. The feedback circuit may include a zeroing amplifier circuit, having an input terminal responsive to the output, for generating the offset adjustment signal. The zeroing amplifier circuit may include a zeroing amplifier offset reduction circuit to minimize the input offset voltage of the zeroing amplifier circuit. The zeroing amplifier circuit may have a zero adjustment input terminal, the zeroing amplifier offset reduction circuit including: a first switching means for applying the offset adjustment signal to the zero adjustment input terminal; and a second switching means for applying a predetermined zeroing signal to the input terminal of the zeroing amplifier circuit. The main amplifier may have an offset adjustment input terminal, the local feedback circuit further including: a first switching means for applying the offset adjustment signal to the offset adjustment input terminal of the main amplifier; a second switching means for applying the output of the main amplifier to the input terminal of the zeroing amplifier circuit; a third switching means for applying a zero input signal to the signal input terminal of the main amplifier; and a fourth switching means for applying the output of the previous amplification stage to the signal input terminal of the main amplifier.
This invention also features a multi-stage, low-offset, fast-recovery, comparator system including: a plurality of self-correcting amplification stages connected in series, each amplification stage having a reset switch connected at its output for returning the output of each amplification stage to the operating input range of the next stage and providing fast response to its next input signal, each amplification stage including: a main amplifier having a signal input terminal and an offset adjustment input, said main amplifier responsive to an input for generating an output; and a local feedback circuit, responsive to the output, for providing an offset adjustment signal to the offset adjustment input to compensate for the local offset voltage of the main amplifier, the local feedback circuit including: a zeroing amplifier circuit, having an input terminal responsive to the output, for generating the offset adjustment signal, said zeroing amplifier circuit including a zeroing amplifier offset reduction circuit to minimize the input offset voltage of the zeroing amplifier.
In a preferred embodiment, the zeroing amplifier circuit may have a zero adjustment input terminal, the zeroing amplifier offset reduction circuit including: a first switching means for applying the offset adjustment signal to the zero adjustment input terminal; and a second switching means for applying a predetermined zeroing signal to the input terminal of the zeroing amplifier. The main amplifier may have an offset adjustment input terminal, the local feedback circuit further including: a first switching means for applying the offset adjustment signal to the offset adjustment input of the main amplifier; a second switching means for applying the output of the main amplifier to the input terminal of the zeroing amplifier; a third switching means for applying a zero input signal to the signal input terminal of the main amplifier; and a fourth switching means for applying the output of the previous amplification stage to the signal input terminal of main amplifier.
This invention also features a method for reducing voltage offset in a single amplification stage of a multistage amplifier, having a zeroing amplifier and a main amplifier including the steps of: reducing the input offset voltage of the zeroing amplifier by a factor essentially equal to the gain of the zeroing amplifier; reducing the input offset voltage of the combined main and zeroing amplifiers by a factor essentially equal to the product of the gains of the main and zeroing amplifier; and amplifying the input signal to the amplification stage in accordance with the gain of the main amplifier to generate an amplified high resolution signal.
In a preferred embodiment, the step of reducing the input offset voltage of the zeroing amplifier may include: applying a zero signal to the input terminals of the zeroing amplifier; connecting the zeroing amplifier output signal, via negative feedback, to the zero input adjustment terminal of the zeroing amplifier; and connecting and storing an adjustment voltage that reduces the input offset voltage of the zeroing amplifier. The step of reducing the input offset voltage of the main amplifier may include: applying a zero signal to the input terminals of the main amplifier; connecting the output of the main amplifier to the input of the xe2x80x9coffset correctedxe2x80x9d zeroing amplifier; connecting the output of the zeroing amplifier, via negative feedback, to the offset adjustment input of the main amplifier; and generating and storing an adjustment voltage that reduces the input offset voltage of the main amplifier. The method may further include the step of returning the amplified high resolution signal to the operating input range of the next amplification stage to provide fast response to its next input signal.